Us_west | Network Design Engin..

Job Description Description:

Skype interview is mandatory please provide the candidates skype ID, VIDEO INTERVIEW IS MANDATORY. NO CPT ALLOWED.

Submit candidates under their legal name and use only Capgemini template Candidate’s photo ID IS MANDATORY FOR ALL CANDIDATES EVEN CITIZENS.

In your submission include: Phone #: Email address: Location (City and State): Relocate: Availability to start: Visa type and expiration date: Hiring Status: C2C/W2/1099QOpen for CTH (y/n): Timeslots for Skype interview (provide Skype ID) Due to additional onboarding requirements, a meet and greet is required for all new hires. Candidates must be willing to go to the closest Capgemini, Client, or offsite location as indicated by project team to meet with a Capgemini team member prior to starting their assignment. If the candidate is not local, travel will be required at the expense of the Capgemini project team (will receive project code for vendor to submit invoices in SAP Fieldglass for reimbursement). If travel is involved, will send travel policy document for the candidate to adhere to

Vendors: If your candidate is selected for interview, you need to take screenshot of candidate and interviewer once interview is initiated. THIS IS NOW MANDATORY FOR ALL INTERVIEWS to confirm candidate is same as person in CV.

Marie Samayoa OBO Tactical Procurement | Procurement Capgemini North America | Guatemala Email: Marie.samayoa@capgemini.com

Job Description: Sr Logic Design Engineer Location: Client Specific Location: Austin, TX No remote, but hybrid option may be negotiated

Good technical leadership skills with ability to guide the CWFs on SoC execution Should have a good understanding of SoC architecture and should be able to map the Arch spec to implementation level details Experience in PCIe and Ethernet IP integration Hands on experience on AMBA based bus protocols Excellent communication skills is a must SoC Design engineer with experience working on SOCs based on ARM Architecture Should be familiar with AMBA based bus protocols like CHI, AXI, AHB, APB etc., Hands on experience in integration of PCIe and Ethernet Ips Good knowledge on design static checks like CDC, RDC, CLP etc., Hands on experience on chip IO integration Desirable to have working knowledge on GIT

• Bachelor’s degree in electrical or computer engineering or related field • 10+ years of experience in Logic (RTL) Design Preferred Qualifications: • Great communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams. • Experience with advanced peripheral bus IP’s such as GPIO, UART, SPI, SW, JTAG, and I2C. • Strong fundamentals in VLSI design • Strong problem-solving and data analysis skills • Strong skills using scripting languages such as Perl, TCL, Python. • Excellent interpersonal skills and able to work with remote teams
• Influence tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach.

Synopsys/Cadence Tools (Preference: 5) Design Compiler (Preference: 5) SpyGlass Tools (Preference: 5) Python (Preference: 3)

Named Job Posting? (if Yes - needs to be approved by SCSC)

try { var fgTooltip = new FG.Tooltip({ element: $('#cf_descz1901221542246011397492e'), text: "To\x20be\x20populated\x20with\x20\x22Yes\x22\x20when\x20Job\x20Seeker\x20to\x20be\x20onboarded\x20is\x20already\x20known\x20at\x20the\x20time\x20of\x20Job\x20Posting\x20creation.\x20Must\x20be\x20approved\x20by\x20SCSC." }).initialize(); } catch(err) {}

Additional Details Global Grade : CNamed Job Posting? (if Yes - needs to be approved by SCSC) : NoRemote work possibility : NoGlobal Role Family : 60239 (P) Cloud InfrastructureGlobal Technical Skills Family : 6246 (T) Network operate & administration TechnologiesLocal Role Name : Sr Logic Design EngineerLocal Skills : Julie SkidmoreLanguages Required: : English