Us_west | Network Design Engin..

Job Description Description:

Skype interview is mandatory please provide the candidates skype ID, VIDEO INTERVIEW IS MANDATORY. NO CPT ALLOWED.

Submit candidates under their legal name and use only Capgemini template Candidate’s photo ID IS MANDATORY FOR ALL CANDIDATES EVEN CITIZENS.

In your submission include: Phone #: Email address: Location (City and State): Relocate: Availability to start: Visa type and expiration date: Hiring Status: C2C/W2/1099QOpen for CTH (y/n): Timeslots for Skype interview (provide Skype ID) Due to additional onboarding requirements, a meet and greet is required for all new hires. Candidates must be willing to go to the closest Capgemini, Client, or offsite location as indicated by project team to meet with a Capgemini team member prior to starting their assignment. If the candidate is not local, travel will be required at the expense of the Capgemini project team (will receive project code for vendor to submit invoices in SAP Fieldglass for reimbursement). If travel is involved, will send travel policy document for the candidate to adhere to

Vendors: If your candidate is selected for interview, you need to take screenshot of candidate and interviewer once interview is initiated. THIS IS NOW MANDATORY FOR ALL INTERVIEWS to confirm candidate is same as person in CV.

Marie Samayoa OBO Tactical Procurement | Procurement Capgemini North America | Guatemala Email: Marie.samayoa@capgemini.com

Job Description: Design Verification Lead Engineer Location: Client Specific Location: Austin, TX No remote, but hybrid option may be negotiated

Ability to Lead fellow CWF and be responsible for delivery Good communication is a must have Proficient leading areas within SOC Verification Familiar with SOC Environment methodology and flows. Ability to debug and also coach fellow team member to debug effectively ARM Processor and CHI working experience PCIE or DDR hands on experience

SOC Verification Experience on ARM Ecosystem PCIE Experience and alsoPCIE-VIP usage experience GLS working experience Proficient in C/System Verilog and UVM Working knowledge of GIT Soft skill -Good Communication and willingness to learn

• 10+ years of experience in pre-silicon design verification • Proficiency in C-shell scripting, Verilog-HDL & System Verilog. • Strong knowledge in SV Assertions, UVM/OVM and functional code coverage. • SOC Verification experience using ARM Cortex Microcontroller is required. • Experience with advanced peripheral bus Verification IP’s such as GPIO, UART, SPI, SW, JTAG, and I2C. • Proficient with Cadence tools such as NCVerilog, NCSIM, Simvision. Experience with linting tools (i.e Spyglass) will be helpful. • Exposure to SDF annotated simulations with good understanding of parasitic delays and timings is required. • Exposure to FPGA programming and FPGA tools will be helpful. • Independent, self-motivated with good analytical & communication skills.

UVM/System Verilog (Preference: 5) Python (Preference: 3) Synopsys/Cadence EDA Verification Tools (Preference: 4

Named Job Posting? (if Yes - needs to be approved by SCSC)

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Additional Details Global Grade : CNamed Job Posting? (if Yes - needs to be approved by SCSC) : NoRemote work possibility : NoGlobal Role Family : 60239 (P) Cloud InfrastructureGlobal Technical Skills Family : 6246 (T) Network operate & administration TechnologiesLocal Role Name : Design Verification Lead EngineerLocal Skills : Julie SkidmoreLanguages Required: : English