Us_west | Mechanical & Physica..

Job Description Description:

Skype interview is mandatory please provide the candidates skype ID, VIDEO INTERVIEW IS MANDATORY. NO CPT ALLOWED.

Submit candidates under their legal name and use only Capgemini template Candidate’s photo ID IS MANDATORY FOR ALL CANDIDATES EVEN CITIZENS.

In your submission include: Phone #: Email address: Location (City and State): Relocate: Availability to start: Visa type and expiration date: Hiring Status: C2C/W2/1099QOpen for CTH (y/n): Timeslots for Skype interview (provide Skype ID) Due to additional onboarding requirements, a meet and greet is required for all new hires. Candidates must be willing to go to the closest Capgemini, Client, or offsite location as indicated by project team to meet with a Capgemini team member prior to starting their assignment. If the candidate is not local, travel will be required at the expense of the Capgemini project team (will receive project code for vendor to submit invoices in SAP Fieldglass for reimbursement). If travel is involved, will send travel policy document for the candidate to adhere to

Vendors: If your candidate is selected for interview, you need to take screenshot of candidate and interviewer once interview is initiated. THIS IS NOW MANDATORY FOR ALL INTERVIEWS to confirm candidate is same as person in CV.

Marie Samayoa OBO Tactical Procurement | Procurement Capgemini North America | Guatemala Email: Marie.samayoa@capgemini.com

Job Description: Physical Design Engineer Location: Longmont, CO (USA) Hybrid option available

• Developing block and SoC timing constraints, full chip STA setup and signoff of multi-corner multi-voltage designs. Synopsys/Cadence EDA tools (Preference: 5)

Job Responsibility • Expertise in understanding constraints and fixing design/timing techniques • Expertise in timing closure (STA) of high frequency blocks • Experience performing detailed synthesis for blocks of high instance counts and complex designs – 1M+ instances and clock frequencies about 1 GHz • Knowledge of signoff closure – Timing with SI and OCV, Power, IR and Physical Verification at both block and chip level • Experience with low power implementation and signoff, power gating, multiple voltage rails, UPF knowledge. • Experience in Block-level and Full-chip integration. • Proficient in Synopsys Fusion Compiler, Design Compiler, Cadence Innovus, PTSi • Experience in Design Automation and UNIX system. • Experience in Tcl/Tk, PERL, Python is a plus.

Desired Skills & Experience: • Must possess 7+ years of hands-on experience in handling block/chip level implementation from RTL to GDSII • Must possess hands on experience in timing closure of blocks and full-chip • Must have handled blocks of sizes 1M instances and above at frequencies higher than 1GHz • Experience in handling lower tech nodes that include 3nm, 5nm, 7nm, 10nm, 16nm, etc. • Must have hands on tape-out experience in lower tech nodes in any of the tools mentioned such as Design Compiler, Fusion Compiler or Innovus. • Must have the ability to think on the spot for quick solutions and work-around at the time of tape-out to hit the schedule on time • Must possess excellent scripting skills – TCL or Perl or Python • Experience in Synthesis and Formal is a MUST • Excellent verbal and written communication skills are required. • Must possess excellent debug skills, analytical skills, and the ability to work independently. • Must be highly motivated and possess excellent team spirit

Named Job Posting? (if Yes - needs to be approved by SCSC)

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Additional Details Global Grade : CNamed Job Posting? (if Yes - needs to be approved by SCSC) : NoRemote work possibility : NoGlobal Role Family : 61405 (P) Products & Systems EngineeringGlobal Technical Skills Family : 60615 (T) Mechanical & Physical EngineeringLocal Role Name : Physical Design EngineerLocal Skills : Julie SkidmoreLanguages Required: : English