Us_west | Electrical\/electronics & Semiconductors Engineer_l2

Job Description Description:

Possible 3 Month CTH | No Fees | Do Not Re-Post | Confidential Skype interview is mandatory please provide the candidates skype ID, VIDEO INTERVIEW IS MANDATORY. NO CPT ALLOWED.

Submit candidates under their legal name and use only Capgemini template Candidate’s photo ID IS MANDATORY FOR ALL CANDIDATES EVEN CITIZENS.

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In your submission include: Phone #: Email address: Location (City and State): Relocate: Availability to start: Visa type and expiration date: Hiring Status: C2C/W2/1099QOpen for CTH (y/n): Timeslots for Skype interview (provide Skype ID)

Due to additional onboarding requirements, a meet and greet is required for all new hires.

Candidates must be willing to go to the closest Capgemini, Client, or offsite location as indicated by the project team to meet with a Capgemini team member prior to starting their assignment.

If the candidate is not local, travel will be required at the expense of the Capgemini project team (will receive project code for vendor to submit invoices in SAP Fieldglass for reimbursement). If travel is involved, will send travel policy document for the candidate to adhere to

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ERM – Miguelangel Buonafina | Capgemini |North America Tel.: +1 888-229-2961 Ext 13578 Miguelangel.buonafina@capgemini.com

Location: Santa Clara, CA

Role: Analog Layout Engineer x3

JOB DESCRIPTION ?Analog Layout Design Engineer

Responsibilities:

Experience with layout of cutting-edge high-performance, high-speed CMOS integrated circuits in older foundry CMOS process nodes in 40nm, 55nm, 65nm and 130nm following best practices from the industry.

• Reviewing and analyzing floorplans and complex circuits with circuit designers

• Running complete set of design verification tools available on AMS blocks

• Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout

• Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area, and power requirements

• Be a great role model, by inspiring and motivating team, and Establishing Effective Organizational Structure and Communication Protocols. Able to Delegate and Empower team along with Effective Time Management.

• Working with the circuit designer or Layout-Lead to plan/schedule work and negotiate any layout trade-offs as needed

Preferred Qualifications:

• 10+ years of experience in analog/mixed-signal layout design of deep submicron CMOS circuits and at least 3+ years of recent experience on advance nodes including FinFET technologies

• Experience with and knowledge of analog/mixed-signal IP (e.g., SERDES PHY, transmitter and receiver, PLL, DDR PHY, ADCs, DACs, LDOs, etc.)

• Experience leading complex layout macros during the full design cycle from floorplan analysis to completion of physical design verification

• Great understanding of CAD flows and tools related to analog/mixed-signal layout design

• Experience crafting well-matched, low noise, and low power analog blocks consisting of transistors, resistors, capacitors, pad IO's, ESD structures, etc.

• High level of proficiency in custom, as well as standard cell-based, floorplanning and hierarchical layout assembly

• Must understand issues of IR drop, RC delay, electro-migration, self-heating and coupling capacitance

• Must recognize failure prone circuit and layout structures, have experience with analog and DFM standard methodologies, and enthusiastically work with circuit designer or layout lead for the best approach to problems

• High level of proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc., reports

• Knowledge of CADENCE or MENTOR GRAPHICS layout tools.

• Excellent interpersonal skills and able to work with remote teams

?Synopsys/Cadence/Mentor Layout tools (Preference: 5)

Python (Preference: 3)

TSMC 7nm or 5nm (Preference: 3)

TSMC 3nm (Preference: 5)?

Named Job Posting? (if Yes - needs to be approved by SCSC)

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Additional Details Global Grade : BNamed Job Posting? (if Yes - needs to be approved by SCSC) : NoRemote work possibility : NoGlobal Role Family : 61405 (P) Products & Systems EngineeringGlobal Technical Skills Family : 60614 (T) Electrical, Electronics & SemiconductorsLocal Role Name : Analog Layout EngineerLocal Skills : Julie SkidmoreLanguages Required: : English